April 18, 2009

ISR - Interrupt Service Routine

When i was in college i always wondered how my mouse clicks where recorded by winamp while it was actually busy playing music.
Only later during my second year in Engineering did i come to know about interrupts. This post is basically a quick and short intro to ISR's.

Interrupts are hardware or software generated events that get registered with the µC/ µP. So when i click my on my mouse, the hardware event generates a signal that goes and gets registered with the processor.
( Note: Actually this process is far more complicated since the interrupt passes through a Interrupt controller etc)

Once it is registered / recognized by the CPU, it then depends on the CPU is configuration whether the interrupt will be processed immediately or will it be kept pending. Processing or servicing of in interrupt is done by saving the current state of the µC and then executing the ISR. The fuzzy word here is current state. It is fuzzy because current state can mean different things in different situations. However, at minimum we know that we would need to save the address of the instrucution which we are currently executing so that after the ISR servicing we can return back to this point.

In real world situations, there can be many events that occur concurrently.

E.g. -> You can right click on the mouse while pressing a key on the keyboard.

How does the CPU handle it all?

The CPU handles this by using an on-chip  or off-chip peripheral unit called the Interrupt Controller. The Interrupt controller is capable of providing priorities to various interrupt sources.

E.g. -> In a Heater control system, the overtemperature event takes higher priority when compared to the User input event.

Apart from Handling the priorities of various interrupt sources, it also ensures that some of the events are masked. E.g you dont want an interrupt to bother you when you are doing some highly critical computation.
In many µC's the interrupt controller is on-chip. Usually, the software during the intialization of the system configures the interrupt controller so that it can prioritize the interrupts etc. In some controller dynamic priority is not available.


E.g. -> A watchdog Interrupt will always take higher priority than a timer interrupt.

So where is the ISR here?

The ISR is a set of instructions that the CPU executes when i detects and acknowledges a said interrupt. The Key word is acknowledges, because in some cases even though the interrupt is detected it will not be acknowledged.

E.g  ->while windows is booting up it might not want to acknowledge any mouse clicks.

At the end of the ISR (i.e the code in the ISR), the CPU returns back to the point where it has broken off to execute the ISR. Note that based on micro-controller architectures this will have differing behaviours when more than one interrupts are in pending state.

The concept of interrupts is very essential and is widely used in almost all embedded applications. Hence, a sound understanding of this concept is essential for anyone who wants to do some kind of embedded programming.



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